TH7834C Datasheet, PDF (4/13 Pages) ATMEL Corporation – Very Highresolution Linear CCD Image Sensor (12000 Pixels)

The four CCD shift registers have separated clocks. The output signal can be, then,
delivered simultaneously or sequentially on the four outputs.
The four CCD shift registers are designed with 4 separated gates. According to the gate
connection, the signal can be read through 2 or 4 output amplifiers.
According to gate connection, 2 or 4 output operating mode can be chosen. In the 4 out-
put operating mode, signals associated to the end pixels of the array (either pixels
number 1, 2 or pixels number 11999, 12000) are delivered first in time and signals corre-
sponding to the center of the line (pixels number 5999, 6000 and 6001, 6002) are
delivered last in time. Thus, external circuitry and processing are needed to combine the
four video outputs and to restore the normal order of the pixels in accordance with their
spatial distribution on the photosensitive line.
Terminal stages for every CCD shift register have separate clock control inputs in order
to speed up the final charge to voltage conversion and reduce the video output settling
time.
Antiblooming and exposure time control functions are provided.
Symmetrical TH7834 package PIN OUT allow to inverted pin 1 and 56 positions without
damage.
To obtain optimal operating mode, separated driving circuits are recommended for each
readout shift register (at least ΦLS and ΦR).
Figure 2. Driving Schematic
Logical signal :ΦL1
ΦL2
Logical signal : ΦL1
ΦL2
VOS2
VOS1
Pins Φ(1,2,3,4)B
Pins Φ(1,2,3,4)D
2 CCD B
Photosensitive line
1 CCD A
6000 6002
5999 6001
Pins F(1,2,3,4)A
Pins F(1,2,3,4)C
CCD D
12000
CCD C
11999
PHI3C
VOS4
VOS3
Logical signal : ΦL1
ΦL2
Logical signal : ΦL1
ΦL2
4 TH7834C
1997A–IMAGE–05/02