AT91SAM9XE128_1 Datasheet, PDF (357/866 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

AT91SAM9XE128/256/512 Preliminary
29.7.2.3
Internal Interrupt Edge Triggered Source
Figure 29-8. Internal Interrupt Edge Triggered Source
MCK
nIRQ
Maximum IRQ Latency = 4.5 Cycles
Peripheral Interrupt
Becomes Active
29.7.2.4
Internal Interrupt Level Sensitive Source
Figure 29-9. Internal Interrupt Level Sensitive Source
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active
29.7.3 Normal Interrupt
29.7.3.1
Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt
conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast
Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ-
ing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the
highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR
(Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have hap-
pened on other interrupt sources since the nIRQ has been asserted, the priority controller
determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The
read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider
that the interrupt has been taken into account by the software.
The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read,
the interrupt with the lowest interrupt source number is serviced first.
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