XMEGAA Datasheet, PDF (353/375 Pages) ATMEL Corporation – 8-bit XMEGAA Microcontroller

XMEGA A
28.12.1
Enabling External Programming Interface
NVM programming from the PDI requires enabling, and this is one the following fashion.
1. Load the RESET register in the PDI with 0x59 - the Reset Signature.
2. Load the correct NVM key in the PDI.
3. Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set.
When the NVMEN bit in the PDI STATUS register is set the NVM interface is active from the
PDI.
28.12.2 NVM Programming
28.12.2.1
Addressing the NVM
When the PDI NVM interface is enabled, all the memories in the device is memory-mapped in
the PDI address space. For the reminder of this section all references to reading and writing
data or program memory addresses from PDI, refer to the memory map as shown in Figure 28-4
on page 352. The PDI is always using byte addressing, hence all memory addresses must be
byte addresses. When filling the Flash or EEPROM page buffers, only the least significant bits of
the address are used to determine locations within the page buffer. Still, the complete memory
mapped address for the Flash or EEPROM page is required to ensure correct address mapping.
28.12.2.2
NVM Busy
During programming (page erase and page write) when the NVM is busy, the complete NVM is
blocked for reading.
28.12.3
NVM Commands
The NVM commands that can be used for accessing the NVM memories from external program-
ming are listed in Table 28-5. This is a super-set of the commands available for self-
programming.
For external programming, the Trigger for Action Triggered Commands is to set the CMDEX bit
in the NVM CTRLA register (CMDEX). The Read Triggered Commands are triggered by a direct
or indirect Load instruction (LDS or LD) from the PDI (PDI Read). The Write Triggered Com-
mands is triggered by a direct or indirect Store instruction (STS or ST) from the PDI (PDI Write).
Section 28.12.3.1 on page 354 through Section 28.12.3.11 on page 357 explains in detail the
algorithm for each NVM operation. The commands are protected by the Lock Bits, and if Read
and Write Lock is set, only the Chip Erase and Flash CRC commands are available.
Table 28-5. NVM commands available for external programming
CMD[6:0]
Commands / Operation
0x00
0x40
No Operation
Chip Erase⁽¹⁾
0x43
Read NVM
Flash Page Buffer
0x23
Load Flash Page Buffer
0x26
Erase Flash Page Buffer
Flash
0x2B
Erase Flash Page
Trigger
-
CMDEX
PDI Read
Change
Protected
-
Y
N
NVM Busy
-
Y
N
PDI Write
N
N
CMDEX
Y
Y
PDI Write
N
Y
8077B–AVR–06/08
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