XMEGAA Datasheet, PDF (198/375 Pages) ATMEL Corporation – 8-bit XMEGAA Microcontroller

XMEGA A
17.10 Register Description - TWI Slave
17.10.1 CTRLA - TWI Slave Control Register A
Bit
+0x00
Read/Write
Initial Value
7
6
INTLVL[1:0]
R/W
R/W
0
0
5
DIEN
R/W
0
4
APIEN
R/W
0
3
ENABLE
R/W
0
2
PIEN
R/W
0
1
PMEN
R/W
0
0
SMEN
R/W
0
CTRLA
• Bit 7:6 - INTLVL[1:0]: TWI Slave Interrupt Level
The Slave Interrupt Level (INTLVL) bits select the interrupt level for the TWI slave interrupts.
• Bit 5 - DIEN: Data Interrupt Enable
Setting the Data Interrupt Enable (DIEN) bit enables the Data Interrupt when the Data Interrupt
Flag (DIF) in the STATUS register is set. The INTLVL bits must be unequal zero for the interrupt
to be generated.
• Bit 4 - APIEN: Address/Stop Interrupt Enable
Setting the Address/Stop Interrupt Enable (APIEN) bit enables the Address/Stop Interrupt when
the Address/Stop Interrupt Flag (APIF) in the STATUS register is set. The INTLVL bits must be
unequal zero for interrupt to be generated.
• Bit 3 - ENABLE: Enable TWI Slave
Setting the Enable TWI Slave (ENABLE) bit enables the TWI slave.
• Bit 2 - PIEN: Stop Interrupt Enable
Setting the Stop Interrupt Enable (PIEN) bit will set the APIF in the STATUS register when a
STOP condition is detected.
• Bit 1 - PMEN: Promiscuous Mode Enable
By setting the Promiscuous Mode Enable (PMEN) bit, the slave address match logic responds to
all received addresses. If this bit is cleared, the address match logic uses the ADDR register to
determine which address to recognize as its own address.
• Bit 0 - SMEN: Smart Mode Enable
Setting the Smart Mode Enable (SMEN) bit enables Smart Mode. When Smart mode is enabled,
the Acknowledge Action, as set by the ACKACT bit in the CTRLB register, is sent immediately
after reading the DATA register.
17.10.2 CTRLB - TWI Slave Control Register B
Bit
7
6
5
4
3
2
1
0
+0x01
-
-
-
-
-
ACKACT
CMD[1:0]
CTRLB
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
8077B–AVR–06/08
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