XMEGAA Datasheet, PDF (243/375 Pages) ATMEL Corporation – 8-bit XMEGAA Microcontroller

ATXMEGA
22. EBI - External Bus Interface
22.1 Features
22.2 Overview
• Supports SRAM up to
– 512K Bytes using 2-port EBI
– 16M Bytes using 3-port EBI
• Supports SDRAM up to
– 128M bit using 3-port EBI
• Four software configurable Chip Selects
• Software configurable Wait State insertion
• Clocked from the Fast Peripheral Clock at two times the CPU speed
22.3 Chip Select
The External Bus Interface (EBI) is the interface for connecting external peripheral and memory
to access it through the data memory space. When the EBI is enabled, data address space out-
side the internal SRAM becomes available using dedicated EBI pins.
The EBI can interface external SRAM, SDRAM, and/or peripherals such as LCD displays and
other memory mapped devices.
The address space, and the number of pins used for the external memory is selectable from 256
bytes (8-bit) and up to 16M bytes (24-bit). Various multiplexing modes for address and data lines
can be selected for optimal use of pins when more or less pins are available for the EBI. The
complete memory will be mapped into one linear data address space continuing from the end of
the internal SRAM, refer to ”Data Memory” on page 21 for details on this.
The EBI has four chip selects with separate configuration. Each can be configured for SRAM,
SRAM Low Pin Count (LPC) or SDRAM.
The EBI is clocked from the Fast Peripheral clock, running up to two times faster than the CPU
and supporting speeds of up to 64 MHz.
For SDRAM both 4-bit and 8-bit SDRAM is supported, and SDRAM configurations such as CAS
Latency and Refresh rate is configurable in software.
For more details on SRAM and SDRAM, and how these memory types are organized and work,
refer to SRAM and SDRAM specific documentation and data sheets. This section only contains
EBI specific details.
22.3.1
The EBI module has four Chip Select lines (CS0 to CS3) where each can be associated with
separate address ranges. The chip selects control which memory or memory mapped external
hardware that is accessed when a given memory address is issued on the EBI. Each Chip
Select has separate configuration, and can be configured for SRAM or SRAM Low Pin Count
(LPC). Chip Select 3 can also be configured for SDRAM.
The data memory address space associated for each chip select is decided by a configurable
base address and address size for each Chip Select.
Base Address
The base address is the lowest address in the address space for a chip select. This decides the
first location in data memory space where the connected memory hardware can be accessed.
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