SAM7SE512_14 Datasheet, PDF (268/682 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

27.8.16 AIC Spurious Interrupt Vector Register
Name:
AIC_SPU
Access:
Read/Write
Reset Value:
0x0
31
30
29
28
27
26
25
24
SIQV
23
22
21
20
19
18
17
16
SIQV
15
14
13
12
11
10
9
8
SIQV
7
6
5
4
3
2
1
0
SIQV
• SIQV: Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in
case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
27.8.17 AIC Debug Control Register
Name:
AIC_DEBUG
Access:
Read/Write
Reset Value:
0x0
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
–
–
–
–
–
7
6
5
4
3
–
–
–
–
–
• PROT: Protection Mode
0 = The Protection Mode is disabled.
1 = The Protection Mode is enabled.
• GMSK: General Mask
0 = The nIRQ and nFIQ lines are normally controlled by the AIC.
1 = The nIRQ and nFIQ lines are tied to their inactive state.
26
25
24
–
–
–
18
17
16
–
–
–
10
9
8
–
–
–
2
1
0
–
GMSK
PROT
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