SAM7SE512_14 Datasheet, PDF (142/682 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

21.6.5.1
address space reserved to NCS4 and/or NCS2 (i.e., between 0x5000 0000 and 0x5FFF FFFF
for NCS4 and between 0x3000 0000 and 0x3FFF FFFF for NCS2).
When multiplexed with CFCE1 and CFCE2 signals, the NCS5 and NCS6 signals become
unavailable. Performing an access within the address space reserved to NCS5 and NCS6 (i.e.,
between 0x6000 0000 and 0x7FFF FFFF) may lead to an unpredictable outcome.
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup-
ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.
I/O Mode, Common Memory Mode, Attribute Memory and True IDE Mode
Within the NCS4 and/or NCS2 address space, the current transfer address is used to distinguish
I/O mode, common memory mode, attribute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated in Figure
21-3.
Figure 21-3. CompactFlash Memory Mapping
CF Address Space
Offset 0x00E0 0000
Offset 0x00C0 0000
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000
True IDE Alternate Mode Space
True IDE Mode Space
I/O Mode Space
Common Memory Mode Space
Attribute Memory Mode Space
21.6.5.2
Note: The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in
True IDE mode).
CFCE1 and CFCE2 signals
To cover all types of access, the SMC must be alternatively set to drive the 8-bit data bus or 16-
bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured
to drive 8-bit memory devices on the corresponding NCS pin (NCS4 and/or NCS2). The DBW
field in the corresponding Chip Select Register of the NCS4 and/or NCS2 address space must
be set as shown in Table 21-4 to enable the required access type.
NUB and NLB are the byte selection signals from SMC and are available when the SMC is set in
Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the Static Memory Controller Section.
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