SAM7SE512_14 Datasheet, PDF (206/682 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

23.6.3
Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t_RP) command and the active/read (t_RCD) com-
mand. This is described in Figure 23-5 below.
Figure 23-5. Read Burst with Boundary Row Access
SDCS
T_RP = 3
T_RCD = 3
CAS = 3
SDCK
A[12:0]
Row n
col a col b col c col d
Row m
col a
col b col c col d col e
RAS
CAS
SDWE
D[31:0]
Dna Dnb Dnc Dnd
Dma Dmb Dmc Dmd Dme
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6222H–ATARM–25-Jan-12