SAM7SE512_14 Datasheet, PDF (121/682 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

SAM7SE512/256/32
20.2.4.1
Write Handshaking
For details on the write handshaking sequence, refer to Figure 20-2and Table 20-4.
Figure 20-2. Parallel Programming Timing, Write Sequence
NCMD
2
3
RDY
NOE
NVALID
DATA[15:0]
1
MODE[3:0]
4
5
Table 20-4. Write Handshake
Step
Programmer Action
1
Sets MODE and DATA signals
2
Clears NCMD signal
3
Waits for RDY low
4
Releases MODE and DATA signals
5
Sets NCMD signal
6
Waits for RDY high
Device Action
Waits for NCMD low
Latches MODE and DATA
Clears RDY signal
Executes command and polls NCMD high
Executes command and polls NCMD high
Sets RDY
Data I/O
Input
Input
Input
Input
Input
Input
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