AT49LD3200 Datasheet, PDF (23/39 Pages) ATMEL Corporation – 32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory

AT49LD3200(B)
Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CL=2
Data
CL=3
CAa
CAb
(1)
DQa0 DQa1 DQa2 DQa3 DQa4
(2)
DQa0 DQa1 DQa2 DQa3 DQa4
(1)
DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
(2)
DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
MR
DQM
Row Active
Read
(1)(2)
Burst Stop Read
Precharge
: Don't Care
Notes: 1. The Burst Stop command is valid at every page burst length. The data bus goes to high-Z after the CAS latency from the
Burst Stop command is issued.
2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min).
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1940B–FLASH–11/01