AT49LD3200 Datasheet, PDF (1/39 Pages) ATMEL Corporation – 32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory

Features
• 3.0V to 3.6V Read/Write
• Burst Read Performance
– <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time
t_SAC = 7 ns
– <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time
t_SAC = 8 ns
– <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time
t_SAC = 9 ns
• MRS Cycle with Address Key Programs
– RAS Latency (1 and 2)
– CAS Latency (2 ~ 8)
– Burst Length: 4, 8
– Burst Type: Sequential and Interleaved
• Word Selectable Organization
– 16 (Word Mode)/x 32 (Double Word Mode)
• Sector Erase Architecture
– Eight 256K Word or 128K Double Word (4-Mbit) Sectors
• Independent Asynchronous Boot Block
– 8K x 16 Bits with Hardware Lockout
• Fast Program Time
– 3-volt, 100 µs per Word/Double Word Typical
– 12-volt, 30 µs per Word/Double Word Typical
• Fast Sector Erase Time
– 2.5 Seconds at 3 Volts
– 1.6 Seconds at 12 Volts
• Low-power Operation
– I_CC Read = 75 mA Typical
• Input and Output Pin Continuity Test Mode Optimizes Off-board Programming
• Package:
– 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability
• LVTTL-compatible Inputs and Outputs
32-megabit
(1M x 32 or
2M x 16)
High-speed
Synchronous
Flash Memory
AT49LD3200
AT49LD3200B
SFlash^™
Description
The AT49LD3200 or AT49LD3200B SFlash^™ is a synchronous, high-bandwidth Flash
memory fabricated with Atmel’s high-performance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
word mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Table). Synchronous design allows precise cycle control. I/O transactions are
possible on every clock cycle. All operations are synchronized to the rising edge of the
system clock. The range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high-band-
width, high-performance memory system applications.
The AT49LD3200B will automatically activate the Asynchronous Boot Block after
power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
vated through Mode Register Set.
The synchronous DRAM interface allows designers to maximize system performance
while eliminating the need to shadow slow asynchronous Flash memory into high-
speed RAM.
The 32-megabit SFlash device is designed to sit on the synchronous memory bus and
operate alongside SDRAM.
Rev. 1940B–FLASH–11/01
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