AT49LD3200 Datasheet, PDF (12/39 Pages) ATMEL Corporation – 32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory

and all the address inputs are ignored. In addition, entering a Mode Register Set com-
mand in the middle of a normal operation results in an illegal state in the
AT49LD3200(B).
Power-up
The following power-up sequence is recommended.
1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other
pins are a NOP condition at the inputs before or along with V_CC (and V_CCQ)
supply.
2. Set WORD to the desired state (prior to any device operation).
3. To change the default Mode Register Set values, perform a Mode Register Set
cycle to program the RAS latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is
ready for operation.
When the above sequence is used for power-up, all outputs will be in high impedance
state. The high impedance of outputs is not guaranteed in any other power-up
sequence.
For AT49LD3200B, Asynchronous Boot Block will be selected after power-up.
Mode Selection Control
Mode selection is controlled by the polarity of WORD pin. WORD should be set to the
desired state during power-up and prior to any device operation. The AT49LD3200(B)
can be organized as either double word wide (x32) or word wide (x16). The organization
is selected via the WORD pin. When WORD is asserted high (V_IH), the double word-
wide organization is selected. When WORD is asserted low (V_IL), the word-wide organi-
zation is selected.
Address Decoding
The address bits required to decode one of the available cell locations out of the total
depth are multiplexed onto the address select pins and latched by externally applying
two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column
address.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of
AT49LD3200(B). It programs the RAS latency, CAS latency, burst length, burst type,
selects product ID Read or activates the Asynchronous Boot Block. For
AT49LD3200(B), the default value of the mode register is defined as array read with
RAS latency = 2, CAS latency = 5, burst length = 4, sequential burst type. When and if
the user wants to change its values, the user must exit from power-down mode and start
Mode Register Set before entering normal operation mode. The mode register is repro-
grammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in
active mode with CKE already high prior to writing the mode register). The state of
address pins A₀ ~ A₇ in the same cycle as CS, RAS, CAS and MR going low is the data
written in the mode register. Three clock cycles are required to complete the program in
the mode register, therefore after a Mode Register Set command is completed, no new
commands can be issued for 3 clock cycles and CS or MR must be high within 3 clock
cycles. The mode register is divided into various fields, depending on functionality. The
burst length field uses A₀ ~ A₁, burst type uses A₂, CAS latency (read latency from col-
umn address) uses A₃ ~ A₅, RAS latency uses A₆ (RAS to CAS delay), array read or
product ID read uses A7. Refer to Mode Register Control Table for specific codes for
various burst lengths, burst types, CAS latencies, RAS latencies, and read modes.
12 AT49LD3200(B)
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