ATA6613C_14 Datasheet, PDF (165/312 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

5.17.1 Overview
A simplified block diagram of the USART transmitter is shown in Figure 5-69. CPU accessible I/O registers and I/O pins are
shown in bold.
Figure 5-69. USART Block Diagram⁽¹⁾
UBRR[H:L]
Baud Rate Generator
OSC
Sync Logic
UDRn (Transmit)
Transmit Shift Register
Parity
Generator
Receive Shift Register
UDR (Receive)
Clock
Recovery
Data
Recovery
Parity
Checker
Clock Generator
Pin
Control
Transmitter
TX
Control
XCKn
Pin
Control
TxDn
Receiver
RX
Control
Pin
Control
RxDn
UCSRnA
UCSRnB
UCSRnC
Note: 1. Refer to Table 5-38 on page 89 for USART0 pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator,
transmitter and receiver. Control registers are shared by all units. The clock generation logic consists of synchronization
logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (transfer clock)
pin is only used by synchronous transfer mode. The transmitter consists of a single write buffer, a serial shift register, parity
generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data
without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data
recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver
includes a parity checker, control logic, a shift register and a two level receive buffer (UDRn). The receiver supports the
same frame formats as the transmitter, and can detect frame error, data overrun and parity errors.
ATA6612C/ATA6613C [DATASHEET] 165
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