ATA6613C_14 Datasheet, PDF (124/312 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

5.14.7.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM1x1:0 = 0 tells the waveform generator that no action on the OC1x register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 5-53 on page 132. For fast PWM mode refer to
Table 5-54 on page 132, and for phase correct and phase and frequency correct PWM refer to Table 5-55 on page 133.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.
5.14.8 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the waveform generation mode (WGM13:0) and compare output mode (COM1x1:0) bits. The compare output mode bits do
not affect the counting sequence, while the waveform generation mode bits do. The COM1x1:0 bits control whether the
PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits
control whether the output should be set, cleared or toggle at a compare match (see Section 5.14.7 “Compare Match Output
Unit” on page 123).
For detailed timing information refer to Section 5.14.9 “Timer/Counter Timing Diagrams” on page 130.
5.14.8.1 Normal Mode
The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter overflow flag (TOV1)
will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1
flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new
counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt
or the prescaler must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
5.14.8.2 Clear Timer on Compare Match (CTC) Mode
In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A
(WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in Figure 5-45. The counter value (TCNT1) increases until a compare match
occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 5-45. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
Period
1
2
3
4
124 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
(COMnA1:0 = 1)