ATA6613C_14 Datasheet, PDF (125/312 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag
according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none
or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new
value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The
counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare
match by setting the compare output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the
port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a
maximum frequency of f_OC1A = f_{clk_I/O}/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the
following equation:
f_OCnA = _2-----×-----N------_×---f-₍-^c--1^l--^k--^_₊--^I--^/-O^O-----C----R----n---A----₎-
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to
0x0000.
5.14.8.3 Fast PWM Mode
The fast pulse width modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM
waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare
(OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting compare output mode
output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast
PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope
operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total
system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum
resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to
MAX). The PWM resolution in bits can be calculated by using the following equation:
R_FPWM = -l-o---g---⁽-l--To---g-O--₍--P-2---₎-⁺-----1---⁾-
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF,
0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15).
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in
Figure 5-46 on page 126. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value
is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between
OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs.
ATA6612C/ATA6613C [DATASHEET] 125
9111L–AUTO–11/14