ATA6613C_14 Datasheet, PDF (163/312 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK frequency) will be doubled when the SPI is in master mode
(see Table 5-70 on page 162). This means that the minimum SCK period will be two CPU clock periods. When the SPI is
configured as slave, the SPI is only guaranteed to work at fosc/4 or lower.
The SPI interface on the Atmel^® ATA6612C/ATA6613C is also used for program memory and EEPROM downloading or
uploading. See Section 5.24.8 “Serial Downloading” on page 267 for serial programming and verification.
5.16.1.5 SPI Data Register – SPDR
Bit
7
6
5
4
3
2
1
0
MSB
LSB
SPDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
Undefined
The SPI data register is a read/write register used for data transfer between the register file and the SPI shift register. Writing
to the register initiates data transmission. Reading the register causes the shift register receive buffer to be read.
5.16.2 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits
CPHA and CPOL. The SPI data transfer formats are shown in Figure 5-67 and Figure 5-68 on page 164. Data bits are
shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 5-68 on page 161 and Table 5-69 on page 162, as done below.
Table 5-71. CPOL Functionality
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
Leading Edge
Sample (rising)
Setup (rising)
Sample (falling)
Setup (falling)
Trailing eDge
Setup (falling)
Sample (falling)
Setup (rising)
Sample (rising)
SPI Mode
0
1
2
3
Figure 5-67. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
Mode 0
SCK (CPOL = 1)
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD =1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
ATA6612C/ATA6613C [DATASHEET] 163
9111L–AUTO–11/14