APW8855 Datasheet, PDF (8/43 Pages) Anpec Electronics Coropration – High Current, High Frequency 7 Outputs Voltage Regulator and Power Management IC for High Performance Tablet and Ultra Notebook Applications

APW8855
11.Pin Description
P IN
NO.
NAME
FUNCTION
1
5 V_ALW_L DO
5V _ALW _LDO Outpu t Pin .
2
5V_ALW_ BYP
5V _ALW _LDO Input Pin. Co nnect to 5V_ ALW Ou tpu t Voltage.
3
5V_ALW _FBP
5V _ALW Output Voltage Fee dback Pin.
4
5V_ ALW_ PWM
5V _ALW PW M Sig nal Outpu t Pin . Co nnect to External po we r stage ’s PWM input pin.
5
1V5 _ALW _IN
1V 5_ALW P WM Reg ulator In put Pin.
6
1V 5_ALW _LX
1V 5_ALW P WM Reg ulator LX Pin . Conne ct to e xterna l i nductor for ou tp ut LC fi lte r.
7
1V5 _ALW_PGND 1V 5_ALW P WM Reg ulator PGND Pin.
8
1 V5_ALW_ FB P
1V 5_ALW P WM Reg ulator Outpu t Vo lta ge Feedb ack Pin.
9
VDDP_ ALW_ GPIO ^{VDDP_ ALW Ou tp ut Sel ect Pin. Pull hi gh for V PPD_ALW=1 .0 5V, pull low for}
VDDP_ ALW=0.95V.
10
VDDP _ALW_FBN VDDP_ ALW Negative Outpu t Feedb ack Pin . Conne ct to VR5 ’s grou nd.
11
VDDP_A LW_FBP VDDP_ ALW Positive Output Fe edba ck Pin. Connect to VR5’s output voltage .
12
VDDP _ALW _PWM VDDP_ ALW PWM Sign al Output P in. Con nect to Exter nal power sta ge’s PWM in put p in.
13
VDD_FCH_S5_ IN VDD_FCH_S5 LDO Reg ulator In put P in.
14
V DD_ FCH_S 5 _OUT VDD_FCH_S5 Outp ut Pi n.
15
VDD_FCH_S5_REFIN VDD_FCH_S5 Tr ack Voltage In put Pin.
VDD_FCH_S5 Tr ack Sel ect Pin. When S5_ MUX=hig h, VDD_FCH_S5 fully tr ack
16
S 5_MUX
VDD_FCH_S5_ REFIN vo lta ge; S5_MUX=lo w, V DD_ FCH_S5 p artially tra ck
VDD_FCH_S5_ REFIN vo lta ge.
17
1 V8_ALW_ FB P
1V 8_ALW P WM Reg ulator Outpu t Vo lta ge Feedb ack Pin.
18
1V8 _ALW_PGND 1V 8_ALW P WM Reg ulator Outpu t PGND Pin.
19
1V 8_ALW _LX
1V 8_ALW P WM Reg ulator Outpu t LX Pin . Conne ct to external in ducto r for ou tp ut LC filter.
20
1V8 _ALW _IN
1V 8_ALW P WM Reg ulator In put Pin.
21
3V3_ALW_BY P
3V 3_ALW_LDO Inpu t Pin . Conne ct to 3V3_ALW Output Vol tag e.
22
3 V3_ALW_ FB P
3V 3_ALW Output Vo ltag e Fe edba ck Pin.
23
3V 3_ALW_PW M
3V 3_ALW P WM S ignal O utp ut Pi n. Conn ect to E xterna l p ower stag e’s PWM inpu t pin .
24
3V3 _ALW_LDO
3V 3_ALW_LDO O utp ut P in.
25
LDO_RTC_IN
L DO_RTC Input Vo lta ge Pin. Provide a 3.3V po wer in to this pin to e nable LDO _RTC Output.
26
LDO_RTC_ OUT L DO_RTC Ou tpu t Voltage Pin .
27
GND
IC An alog Gr ound .
28
V SYS
IC Powe r Inp ut Pin.
29
I2CDATA
I2C Data Con nection Pin.
30
I2CCLK
I2C Clock Sig nal Pin.
31
PO K
Power Good Ind icato r. Conn ect a resistor from POK to a pull- high voltage.
32
CTL
System P ower Sta te Control Pin . Pul l CTL h igh to e nable V R1/2 /3 /4/5/7.
Exp osed
P ad
P GND
IC Power Gro und
Copyright © ANPEC Electronics Corp.
8
Rev. A.1 - Dec., 2015
www.anpec.com.tw