APW8855 Datasheet, PDF (33/43 Pages) Anpec Electronics Coropration – High Current, High Frequency 7 Outputs Voltage Regulator and Power Management IC for High Performance Tablet and Ultra Notebook Applications

APW8855
15.2 I2C Function Description(Cont.)
Protocol
Reads from PMIC registers follow the “combined protocol” as described in the I2C specification, in which the first byte
written is the register offset to be read, and the first byte read (after a repeat START condition) is the data from that
register offset. See the figures below for details. The following diagrams capture the different high-speed and fast-
speed transaction format/protocol.
S
7bit Slave
Address
R/W A 8bit Address A
8bit Data
AP
7'h6E
‘0’
Reg. Address
Reg. Data
Master to Slave
Slave to Master
A = Acknowledge ( SDA LOW )
A = Not Acknowledge ( SDA HIGH )
S = START Condition
P = STOP Condition
Figure 1. I2C Fast Speed / Fast Speed Plus Single Byte Write
S
7bit Slave
Address
R/W A
8bit Reg.
Address
A
8bit Data A
8bit Data A P
7'h 6E
‘0’
Master to Slave
Slave to Master
Reg. First Byte
Data
Reg. Last Byte
Data
A = Acknowledge ( SDA LOW )
A = Not Acknowledge ( SDA HIGH )
S = START Condition
P = STOP Condition
Figure 2. I2C Fast Speed / Fast Speed Plus Multiple Byte Write
S
7bit Slave
Address
R/W A 8bit Address A Sr
7bit Slave
Address
R/W A
8bit Data
AP
7'h 6E
‘0’
Reg. Address
7'h 6E
‘1’
Reg. Data
Master to Slave
Slave to Master
A = Acknowledge ( SDA LOW )
A = Not Acknowledge ( SDA HIGH )
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
Figure 3. I2C Fast Speed / Fast Speed Plus Single Byte Read
Copyright © ANPEC Electronics Corp.
33
Rev. A.1 - Dec., 2015
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