APW8855 Datasheet, PDF (28/43 Pages) Anpec Electronics Coropration – High Current, High Frequency 7 Outputs Voltage Regulator and Power Management IC for High Performance Tablet and Ultra Notebook Applications

APW8855
14.6 VR5 Register Table
Address
Field Name
Da ta B it
Bit Name
Re ad/Write
Power On Defaul t
Bit Na me
VDDP_A LW_V SEL
0 x09
VDDP_ ALW DAC [7: 0]
D7
D6
D5
D4
D3
D2
D1
D0
V DDP_ALW_VS EL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
1
1
0
Bit De finition
00 h : shutdown
01 h : VR5 Voltage = 50 0mV.
02 h : VR5 Voltage = 51 0mV.
03 h : VR5 Voltage = 52 0mV.
…
2e h : VR5 Voltage = 95 0mV (De fa ult)
….
65 h : VR5 Voltage = 15 00mV.
66 h~ffh : Reserved
Addres s
Fie ld Na me
Data B it
Bit Na me
Read/Write
Po wer On De fa ult
Bit Name
VDDP_ ALW_EN
VDDP_ ALW_SEL
VDDP_ ALW_ FSW _SEL
VDDP_ ALW_SLEW
0x 0A
V DDP_ALW CO NTROL [7:0]
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
VDDP_ ALW_S LEW
R/W
R/W
V DDP_ALW_FSW
_SE L
R/W
R/W
VDDP_A L VDDP _AL
W__ SEL W__ EN
R/W
R/W
0
0
1
0
0
0
Bit Definition
0: V R5 o ff (De fau lt)
1: V R4 on
0: V R5 o n/off i s controlle d by CTL, an d o utput voltage is control by VDDP_ ALW_ GPIO. (Defa ult)
1: V R5 o n/off i s controlle d by VDDP_A LW_E N State a nd output vo ltag e i s control by
VDD P_A LW_V SEL.
00 : FSW = 0.3MHz at PWM mod e.
01 : FSW = 0.6MHz at PWM mod e.
10 : FSW = 0.5MHz at PWM mod e. (Defau lt)
11 : FSW = 0.8MHz a t PWM mode.
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s
Copyright © ANPEC Electronics Corp.
28
Rev. A.1 - Dec., 2015
www.anpec.com.tw