ACD2203 Datasheet, PDF (7/24 Pages) ANADIGICS, Inc – CATV/TV/Video Downconverter with Dual Synthesizer

PARAMETER
Table 6: Digital 2-Wire Interface Specifications
(TA = +25 °C, VDD = +5 VDC, ref. Figure 4)
SYMBOL
MIN
MAX
CLK Frequency
fCLK
1
400
Logic High Input (pins 11, 12)
VH
2.0
-
Logic Low Input (pins 11, 12)
VL
-
0.8
Logic Input Current Consumption
(pins 11, 12)
ILOG
-
10
Address Select Input Current
Consumption (pin 10)
IAS
-
10
Data Sink Current ⁽²⁾
IAK
-
4.0
Bus Free Time between a STOP and
START Condition
tBUF
1.3
-
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
tHD;STA
0.6
-
generated.
LOW period of CLK
tLOW
1.3
-
HIGH period of CLK
tHIGH
0.6
-
Set-up Time for a Repeated START
Condition
tSU;STA
0.6
-
Data Hold Time (for 2-wire bus devices) tHD;DAT
0.0
0.9
Data Set-up Time
tSU;DAT
100
-
Rise Time of DATA and CLK Signals
tR
20 + 0.1Cb ⁽¹⁾ 300
Fall Time of Data and CLK Signals
tF
20 + 0.1Cb ⁽¹⁾ 300
Set-up Time for STOP Condition
tSU;STO
0.6
-
Capacitive Load for Each Bus Line
Cb
-
400
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum VH and maximum VL levels.
ACD2203
UNIT
kHz
V
V
µA
µA
mA
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
DATA
tF
tLOW
tR
CLK
t t HD;STA
HD;DAT
S
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
tHIGH
tSU;STA
Sr
Figure 4: Serial 2-Wire Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
tSU;STO
P
S
7