ACD2203 Datasheet, PDF (12/24 Pages) ANADIGICS, Inc – CATV/TV/Video Downconverter with Dual Synthesizer

ACD2203
Table 7: Address Select Decoding
(TA = +25 °C ⁽¹⁾, VDD = +5 VDC)
VOLTAGE ON PIN
10, AS
C (BINARY 12)
AS2 AS1
B7 B6 B5 B4 B3 B2 B1 B0
HEX
DECIMAL
VSS < AS < 0.8V
1 1 0 0 0 0 1 0 C2
194
1.1V < AS < 1.7V 1 1 0 0 0 0 0 0 C0
192
2.1V < AS < 2.7V 1 1 0 0 0 1 0 0 C4
196
3.15V < AS < 3.65V 1 1 0 0 0 0 0 0 C0
192
4.2V < AS < VDD
1 1 0 0 0 1 1 0 C6
198
Notes:
(1) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is
+25 °C, using the PC Board Layout shown in Figures 24-26.
allow a wide range of output frequencies. The 24-bit
registers that control the dividers and other functions
are each segmented into three 8-bit data words, and
are programmed via the two-wire interface.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 8 indicates the register select bit settings used
to program each of the available registers.
Table 8: Register Select Bits
SELECT
BITS
SS
2
1
DESTINATION REGISTER FOR
SERIAL DATA
0 0 Reference Divider Register for PLL2
0
1 Main Divider Register for PLL2
1 0 Reference Divider Register for PLL1
1 1 Main Divider Register for PLL1
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 11. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 12, and the seven
A Counter bits and allowed values are shown in
Table 13. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the variables
are defined in Table 14:
fVCO = N x fOSC/R, where N = [(P x B) + A]
where:
N = [(P x B) + A]
f_VCO is the desired output frequency
B is the divide ratio of the B counter (3 to 2047)
A is the divide ratio of the A counter (0<A<P, A<B)
f_OSC is the frequency of the reference oscillator
R is the divide ratio of the R counter (3 to 32767)
P is the preset modulus of the prescalar (P=64).
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 9. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 10.
12
PRELIMINARY DATA SHEET - Rev 1.3
12/2003