ACD2203 Datasheet, PDF (11/24 Pages) ANADIGICS, Inc – CATV/TV/Video Downconverter with Dual Synthesizer

ACD2203
LOGIC PROGRAMMING
The ACD2203 includes an interface for a two-wire
serial data control bus that ANADIGICS has
developed for use with its dual PLL synthesizers.
This interface saves one connection between the
host and the dual synthesizer, compared to a
standard CLOCK-DATA-ENABLE three-wire
interface. The interface is optimized for applications
in which the dual synthesizer is a slave receiver
device. Hosts that conform to the I²C-Bus
Specification standard can be used to program a
dual PLL that uses this interface.
Physical Interface
The two-wire interface consists of two digital signal
lines, CLOCK and DATA. The speed of the interface
is nominally 400 kbits/sec. For data transmission,
the signal on the DATA line must be stable when the
CLOCK signal is high, and the state of the data must
change only while the CLOCK signal is low. A logic
level transition on the DATA line during a high
CLOCK signal indicates the beginning or end of a
data transmission, as specified in the following
sections and shown in Figure 21.
Start
Indicator:
CLOCK
DATA
Stop
Indicator:
CLOCK
DATA
Figure 21: Transmission Indicators
Addressing The Dual PLL
The dual PLL monitors the CLOCK and DATA
signals for a Start indication from the host. A Start is
indicated by a high-to-low transition of the DATA
signal while the CLOCK signal is high. Immediately
following the Start indicator, the host sends an 8-bit
address word to the dual PLL. The 8-bit word
required to address the dual PLL is programmable
via a DC voltage level applied to the address select
pin. For example, a voltage of 4V<AS<5V
corresponds to a value of C6h, or 11000110b. (The
MSB is sent first, LSB last.) The Address Select pin
(10) decodes an analog voltage input into two digital
logic output bits AS1 and AS2. The level of a DC
voltage applied to this pin determines the two-bit
logic state, AS2 and AS1 to address the synthesizer.
The software must be programmed with the
corresponding decimal equivalent of the 8b word
selected, as shown in Table 7. Once the dual PLL
has recognized the Start indicator and the
correct address word, it sends an address
acknowledgement to the host by pulling the DATA
line low for one clock pulse. The host can then begin
to send data to program the dual PLL.
Sending Data
After receiving the address byte acknowledgement
from the dual PLL, the host begins sending
programming data in 8-bit words. The MSB is sent
first, and the LSB last. Following the receipt of each
8-bit data word, the dual PLL acknowledges receipt
by pulling the DATA line low for one clock pulse. The
data acknowledgement tells the host it may send
the next data word. For the dual PLL, each group of
three data words (24 bits total) is a significant block
of information used to program one of four registers,
as described in “Programming the Dual PLL.”
Completing Data Transmissions
After sending the final data word, the host sends a
Stop indicator to mark the end of data transmission.
A Stop is indicated by a low-to-high transition of the
DATA signal while the CLOCK signal is held high.
After receiving the Stop indicator, the dual PLL ceases
to send further acknowledgements and begins to
monitor the CLOCK and DATA signals for the next
Start indicator.
Note: The Stop indicator does not directly control
when the programming data is latched or takes
effect; the data takes effect immediately following
the receipt of each three-word block of data, which
represents a complete 24-bit divider register.
Resending Data
If, for some reason, the data transmission fails or is
interrupted, and the dual PLL fails to send an
address word or data word acknowledgement to
the host, the host can resend the data. To resend
data, a new Start indicator and address word must
be sent prior to any data words.
Programming The Dual PLL
Each synthesizer in the dual PLL contains
programmable Reference and Main dividers, which
PRELIMINARY DATA SHEET - Rev 1.3
11
12/2003