ACD2203 Datasheet, PDF (16/24 Pages) ANADIGICS, Inc – CATV/TV/Video Downconverter with Dual Synthesizer

ACD2203
Table 17: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
MSB
LSB
Data Word
FIRST DATA WORD
SECOND DATA WORD
THIRD DATA WORD
Register Bit ^{24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1}
Function
Dummy/
Spacer
Program Mode
Reference Divider Divide Ratio, R
Select
Data
X
2
X
1
D
5
D
4
D
3
D
2
D
1
RRRRRRR
15 14 13 12 11 10 9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
PLL2 _{0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0}
PLL1 ^{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0}
Table 18: PLL1 and PLL2 Main Divider Register Bits
MSB
for Synthesizer Programming Example
LSB
Data Word
FIRST DATA WORD
SECOND DATA WORD
THIRD DATA WORD
Register Bit ^{24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1}
Function
Dummy/
Spacer
Program
Mode
B Counter
A Counter
Select
Data ^{X X C C B B B B B B B B B B B A A A A A A A S S}
2 1 2 1 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 2 1
PLL2 _{0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1}
PLL1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1
16
PRELIMINARY DATA SHEET - Rev 1.3
12/2003