TCS3400 Datasheet, PDF (16/35 Pages) ams AG – Single Device Integrated Optical Solution

TCS3400 − Register Description
Figure 21:
RGBC Integration Time Register
RGBC Integration Time Register (ATIME 0x81)
The ATIME register controls the internal integration time of the
RGBC channel ADCs. Upon power up, the RGBC time register is
set to 0xFF.
The maximum (or saturation) count value can be calculated
based upon the integration time cycles as follows:
min [CYCLES * 1024, 65535]
Field
ATIME
Bits
7:0
Value
0xFF
0xF6
0xDB
0xC0
0x00
Description
Cycles
Time
1
2.78 ms
10
27.8 ms
37
103 ms
64
178 ms
256
712 ms
Max Count
1024
10240
37888
65535
65535
Figure 22:
Wait Time Register
Wait Time Register (WTIME 0x83)
The WTIME controls the amount of time in a low power mode.
It is set 2.78 ms increments unless the WLONG bit is asserted in
which case the wait times are 12× longer. WTIME is
programmed as a 2’s complement number. Upon power up, the
wait time register is set to 0xFF.
Field
WTIME
Description
Bits
Register Value Wait Time
Time
(WLONG=0)
Time
(WLONG=1)
0xFF
1
2.78 ms
0.03 s
7:0
0xAB
85
236 ms
2.84 s
0x00
256
712 ms
8.54 s
Note(s):
1. The wait time register should be configured before AEN is asserted.
Page 16
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ams Datasheet
[v1-01] 2016-Apr-13