A43E06161_15 Datasheet, PDF (36/48 Pages) AMIC Technology – 512K X 16 Bit X 2 Banks Synchronous DRAM

A43E06161
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0
CLOCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
BA
A10/AP
Ra
Cb
Cc
WE
DQM
* Note 1
DQ
Qa0 Qa1
Qa2
Qa3
Qb0 Qb1
Dc0
Dc2
tSHZ
tSHZ
Row Active Read
Clock
Suspension
Read
* Note : DQM needed to prevent bus contention.
Read DQM
Write
DQM
Write
Clock
Suspension
: Don't care
PRELIMINARY (February, 2008, Version 0.3)
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AMIC Technology, Corp.