A43E06161_15 Datasheet, PDF (31/48 Pages) AMIC Technology – 512K X 16 Bit X 2 Banks Synchronous DRAM

Read & Write Cycle with Auto Precharge II @Burst Length=4
A43E06161
0
CLOCK
CKE
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
High
RAS
CAS
ADDR
Ra
BA
A10/AP
Ra
WE
Rb Ca
Cb
Rb
Ra
Ca
Ra
DQM
DQ
(CL=2)
DQ
(CL=3)
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3
Da0 Da1
Da0 Da1
Row Active
(A-Bank)
Read with
Auto Pre
Charge
(A-Bank)
Row Active
(B-Bank)
Read without
Auto Precharge
(B-Bank)
Auto Precharge
Strart Point
(A-Bank) *Note 1
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don't care
* Note : When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto
precharge will start at B Bank read command input point.
- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
PRELIMINARY (February, 2008, Version 0.3)
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AMIC Technology, Corp.