A43E06161_15 Datasheet, PDF (33/48 Pages) AMIC Technology – 512K X 16 Bit X 2 Banks Synchronous DRAM

A43E06161
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Burst Length = Full Page)
0
CLOCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
BA
A10/AP
RAa
CAa
* Note 1
CAb
* Note 1
WE
DQM
DQ
(CL=2)
DQ
(CL=3)
* Note 2
1
QAa0 QAa1 QAa2 QAa3 QAa4
2
QAa0 QAa1 QAa2 QAa3 QAa4
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
2
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
PRELIMINARY (February, 2008, Version 0.3)
32
AMIC Technology, Corp.