A43E06161_15 Datasheet, PDF (16/48 Pages) AMIC Technology – 512K X 16 Bit X 2 Banks Synchronous DRAM

3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)^{Note 1}
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
RD RD
AB
QA0 QB0 QB1 QB2 QB3
tCCD
Note2
QA0 QB0 QB1 QB2 QB3
A43E06161
2) Write interrupted by Write (BL =2)
CLK
CMD
ADD
DQ
WR WR
tCCD Note2
AB
DA0 DB0
tCDL
Note3
DB1
3) Write interrupted by Read (BL =2)
DQ(CL2)
DQ(CL3)
WR RD
tCCD Note2
AB
DA0
DA0
tCDL
Note3
QB0 QB1
QB0 QB1
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.
By “ CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (= 1CLK).
PRELIMINARY (February, 2008, Version 0.3)
15
AMIC Technology, Corp.