AMIS-710616 Datasheet, PDF (4/19 Pages) AMI SEMICONDUCTOR – CIS PCB

AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
(11) Modulation transfer function depends on the optical system. Since this system relies on the users optical system, it was not measured. Referring back to Note
5, measurements on Up, all notes that reference the optical measurements apply to MTF measurements as well. Using a conservative engineering estimate,
the sensor’s MTF is in excess of 70 percent at the optical Nyquest frequency.
7.0 Electrical Timing Characteristics
7.1 Clock Amplitude and Duty Characteristics
Table 7-1: Clock Amplitude and Duty Characteristics (Ta =25^°C)
Item
Clock input voltage
Clock input current
Clock frequency
Symbol
VIH ⁽¹⁾
VIL ⁽¹⁾
IIH ⁽¹⁾
IIL ⁽¹⁾
Freq ⁽²⁾
Condition
For values see
the notes
Min.
0.100
Specification
Typ.
See Note (1) for values
See Note (1) for values
5.0
Max.
6.0
Units
MHz
Line read time
Tint ⁽³⁾
160
192
1000
µs
Clock pulse duty cycle
Ratio = tw/ to ⁽⁴⁾
25
50
75
%
Notes:
(1) These CP and SP values are compatible with CMOS 74HCXX series logic devices.
(2) Freq is not only the clock frequency, but is also equal to the pixel sample rate. See not 2 under Table 6.1.
(3) Tint is the line scan read time, which depends on the interval between the SP entries. See Note 1 under Table 6.1. The longest integration time is determined
by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can
use his discretion to determine the desired tolerance level for the given system.
(4) The definition for the symbols used in the ratio is defined in Section 7.2.
7.2 Clock Timing Characteristics
This table defines the symbols used in the timing diagram (Figure 3). It is for a single video section, however it applies to all eight video
sections. Accordingly, the system-timing diagram is a composition of this timing diagram repeated eight times, with all waveforms in
parallel, so electrically the system produces pixels from all eight video sections simultaneously.
Table 7-2: Clock Timing Characteristics
Item
Clock cycle time⁽²⁾
Clock pulse width⁽²⁾
Clock duty cycle⁽²⁾
Symbol
to
tw
duty
Min.
0.1666
25
Typ.
0.200
0.100
50
Max.
10
75
Units
µs
ns
%
Prohibit crossing time of SP
tprh
30
ns
Data setup time
tds
30
ns
Data hold time
tdh
25
ns
Signal delay time
Signal sample time
tdl
tsmp⁽³⁾
125
75
ns
ns
Signal fall time
Recommended SP generation
tsigf
Tonoff⁽⁴⁾
75
ns
Notes:
(1) This applies to the whole chart. All of the symbol definitions in Table 7-2 are used in Figure 3. For the complete system, there are only two clocks, CP and SP and
their logic levels are compatible with CMOS 74HCXX series logic devices.
(2) See the notes on clock periods (the inverse of freq) and their duty cycles under Table 5-1 Notes 3 and 4.
(3) See AMIS-720639 data sheet Page 6, Table 6A, Note 6.
(4) This is the recommended method for SP generation because the shift register loads only on the falling edge.
AMI Semiconductor – July 06, M-20595-001
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