AM79C976 Datasheet, PDF (80/309 Pages) Advanced Micro Devices – PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller

PRELIMINARY
Table 9. VLAN Tag Control Command
TCC
(TMD2[17:16])
Action
00
Transmit data in buffer unaltered
01
Delete Tag Header
10
Insert Tag Header containing TCI
field from descriptor.
11
Replace TCI field from buffer with TCI
data from descriptor.
Table 10. VLAN Tag Type
TT
(RMD1[19:18])
Description
00
Reserved
01
Frame is untagged
10
Frame is priority-tagged
11
Frame is VLAN-tagged
Loopback Operation
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the control-
ler receives its own transmissions. The controller pro-
vides two basic types of loopback. In internal loopback
mode, the transmitted data is looped back to the re-
ceiver inside the controller without actually transmitting
any data to the external network. The receiver will
move the received data to the next receive buffer,
where it can be examined by software. Alternatively, in
external loopback mode, data can be transmitted to
and received from the external network.
The external loopback through the MII requires a two-
step operation. The external PHY must be placed into
a loop-back mode by writing to the PHY Access Regis-
ter. Then the Am79C976 controller must be placed into
an external loopback mode by setting EXLOOP
(CMD2, bit 3).
The internal loopback through the MII is controlled by
INLOOP (CMD2, bit 4). When set to 1, this bit will
cause the internal portion of the MII data port to loop-
back on itself. The MII management port (MDC, MDIO)
is unaffected by the INLOOP bit.
The internal MII interface is mapped in the following
way:
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During the internal loopback, the TX_EN and TXD pins
will be active. Internal loopback should not be used on
a live network because collisions will not be handled
correctly. The wire should be disconnected or the PHY
isolated before using internal loopback.
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All transmit and receive function programming, such as
automatic transmit padding and receive pad stripping,
operates identically in loopback as in normal operation.
Runt Packet Accept is internally enabled regardless of
the state of the RPA bit in CSR124 when any loopback
mode is invoked. This is for backwards compatibility
with the C-LANCE (Am79C90) software.
The C-LANCE controller and the half-duplex members
of the PCnet family of devices place certain restrictions
on FCS generation and checking, and on testing multi-
cast address detection. Since the Am79C976 controller
has two FCS generators, these restrictions do not
apply to the Am79C976 controller. On receive, the
Am79C976 controller provides true FCS status. The
descriptor for a frame with an FCS error will have the
FCS bit (RMD1, bit 27) set to 1. The FCS generator on
the transmit side can still be disabled by setting DXMT-
FCS (CSR15, bit 3) to 1.
In internal loopback operation, the Am79C976 control-
ler provides a special mode to test the collision logic.
When FCOLL (CSR15, bit 4) is set to 1, a collision is
forced during every transmission attempt. This will re-
sult in a Retry error.
Full-Duplex Operation
The Am79C976 controller supports full-duplex opera-
tion on both network interfaces. Full-duplex operation
allows simultaneous transmit and receive activity on the
TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex
operation is enabled by the FDEN bit located in BCR9
for all ports. Full-duplex operation is also enabled
through Auto-Negotiation when DANAS (BCR 32, bit 7)
is not enabled on the MII port and the ASEL bit is set,
and both the external PHY and its link partner are ca-
pable of Auto-Negotiation and full-duplex operation.
When operating in full-duplex mode, the following
changes to the device operation are made:
The MAC engine changes for full-duplex operation are
as follows:
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80
Am79C976
8/01/00