AM79C976 Datasheet, PDF (61/309 Pages) Advanced Micro Devices – PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller

PRELIMINARY
should not mix the CSR5/CSR7 method with the CMD0
method.
For compatibility with other PCnet family devices, after
the SPND bit in CSR5 is set, it will read back a one only
after the suspend operation is complete, that is, after
both TX_SUSPENDED and RX_SUSPENDED in
STAT0 have been set. It is recommended that when
software polls this register that a delay be inserted be-
tween polls. Continuous polling will reduce the bus
bandwidth available to the Am79C976 controller and
will delay the completion of the suspend operation.
It is recommended that software use the SPNDINT in-
terrupt to determine when the Am79C976 controller
has suspended after one or more suspend bits have
been set. This results in the least competition for the
PCI bus and thus the shortest time from setting of a
suspend bit until completion of the suspend operation.
Clearing the RUN bit in CMD0 will generate a pulse that
will clear all the suspend command and status bits
(TX_SPND, RX_SPND, TX_FAST_SPND and
RX_FAST_SPND in CMD0, TX_SUSPENDED and
RX_SUSPENDED in STAT0, SPND in CSR5 and DRX
and DTX in CSR15). The RX_SPND or TX_SPND bits
may then be set while RUN is cleared. When RUN is
subsequently set, the suspend bit will remain set and
the corresponding operation (transmit or receive) will
be disabled. Since the suspend bit will be cleared when
RUN is cleared, this must be done each time RUN is
set. Since the suspend bits and RUN are in the same
register (CMD0), the suspend bit may be set at the
same time that RUN is set.
For compatibility with other PCnet family devices, set-
ting the STOP bit in CSR0 will also clear the SPND bit
in CSR5. While STOP is set, the DRX or DTX bits in
CSR15 may be set. When the STRT bit in CSR0 is sub-
sequently set, the corresponding operation will be dis-
abled. Since the bits are all cleared when STOP is set,
CSR15 must be written (either directly or indirectly via
the DMA initialization) each time before STRT is set
again.
The suspend bits in CMD0 and STAT0 are equivalent
but not identical to the suspend bits in CSR5, CSR7
and CSR15. Software should use one set of bits or the
other and not mix them. The SPNDINT bit in INT0 has
no equivalent in the CSR registers, so this bit may be
used to detect the completion of a suspend operation
initiated by the SPND bit in CSR5.
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Descriptor management is accomplished through mes-
sage descriptor entries organized as ring structures in
memory. There are two descriptor rings, one for trans-
mit and one for receive. Each descriptor describes a
single buffer. A frame may occupy one or more buffers.
If multiple buffers are used, this is referred to as buffer
chaining.
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Each descriptor ring must occupy a contiguous area of
memory. During initialization, the user-defined base
address for the transmit and receive descriptor rings,
as well as the number of entries contained in the de-
scriptor rings are set up. The programming of the soft-
ware style (SWSTYLE, BCR20, bits 7-0) affects the
way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of 0, the de-
scriptor rings are backwards compatible with the
Am79C90 C-LANCE and the Am79C96x PCnet-ISA
family. The descriptor ring base addresses must be
aligned to 8-byte boundaries. Each ring entry contains
a subset of the three 32-bit transmit or receive mes-
sage descriptors that are organized as four 16-bit
structures (SSIZE32 (BCR20, bit 8) is set to 0). Note
that even though the Am79C976 controller treats the
descriptor entries as 16-bit structures, it will always
perform 32-bit bus transfers to access the descriptor
entries. The value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus mas-
ter transfers.
When SWSTYLE is set to 2, 3, or 4, the descriptor ring
base addresses must be aligned to 16-byte bound-
aries. Each ring entry is organized as three 32-bit mes-
sage descriptors (SSIZE32 (BCR20, bit 8) is set to 1).
The fourth DWord is reserved for user software pur-
poses. When SWSTYLE is set to 3, 4, or 5, the order of
the message descriptors is optimized to allow read and
write access in burst mode.
When SWSTYLE is set to 5, the descriptor ring base
addresses must be aligned to a 32-byte boundary.
Each ring entry is organized as eight 32-bit message
descriptors (SSIZE32 (BCR20, bit 8) is set to 1).
Descriptor ring lengths can be set up either by writing
directly to the transmit and receive ring length registers
(CSR76, CSR78) or by using the initialization block. If
the initialization block is used to set up ring lengths, the
ring lengths are restricted to powers of two that are less
than or equal to 128 if SWSTYLE is 0 or 512 if SW-
STYLE is 2 or 3. However, ring lengths of any size up
to 65535 descriptors can be set up by writing directly to
the transmit and receive ring length registers.
The initialization block can not be used if SWSTYLE is
4 or 5. The descriptor ring lengths must be initialized by
writing directly to the appropriate registers.
Each ring entry contains the following information:
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Am79C976
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