AM79C976 Datasheet, PDF (181/309 Pages) Advanced Micro Devices – PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller

PRELIMINARY
comes out of suspend mode. The
Am79C976 controller will contin-
ue at the transmit and receive de-
scriptor ring locations, from
where it had left, when it entered
the suspend mode.
Read/Write accessible. SPND is
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
&65 5HVHUYHG
Bit Name
Description
31-0 RES
Reserved locations. Written as
zeros and read as undefined.
&65 ([WHQGHG &RQWURO DQG ,QWHUUXSW 
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
Bit Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15 FASTSPNDE
Fast Suspend Enable. When
FASTSPNDE is set to 1, the
Am79C976 controller performs a
fast suspend whenever the
SPND bit is set.
When a fast suspend is request-
ed, the Am79C976 controller per-
forms a quick entry into the
suspend mode. At the time the
SPND bit is set, the Am79C976
controller will complete the DMA
process of any transmit and/or re-
ceive packet that had already be- _{14 RES}
gun DMA activity. In addition, any
transmit packet that had started
transmission will be fully transmit- 13 RDMD
ted and any receive packet that
had begun reception will be fully
received. However, no additional
packets will be transmitted or re-
ceived and no additional transmit
or receive DMA activity will begin.
Hence, the Am79C976 controller
may enter the suspend mode
with transmit and/or receive
packets still in the FIFOs or the
SRAM.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C976
controller may take longer before
entering the suspend mode. At
the time the SPND bit is set, the
Am79C976 controller will com-
plete the DMA process of a trans-
mit packet if it had already begun
and the Am79C976 controller will
completely receive a receive
packet if it had already begun.
Additionally, all transmit packets
stored in the transmit FIFOs and
the transmit buffer area in the
SRAM (if one is enabled) will be
transmitted and all receive pack-
ets stored in the receive FIFOs,
and the receive buffer area in the
SRAM (if one is enabled) will be
transferred into system memory.
Since the FIFO and SRAM con-
tents are flushed, it may take
much longer before the
Am79C976 controller enters the
suspend mode. The amount of
time that it takes depends on
many factors including the size of
the SRAM, bus latency, and net-
work traffic level.
When a write to CSR5 is per-
formed with bit 0 (SPND) set to 1,
the value that is simultaneously
written to FASTSPNDE is used to
determine which approach is
used to enter suspend mode.
Read/Write accessible. FASTSP-
NDE is cleared by H_RESET,
S_RESET or by setting the STOP
bit.
Reserved location. Written as ze-
ro, read as undefined.
Receive Demand, when set,
causes the Buffer Management
Unit to access the Receive De-
scriptor Ring without waiting for
the chain poll-time counter to ex-
pire.
Read/Write accessible. RDMD is
set by writing a 1. Writing a 0 has
no effect. RDMD will be cleared
by the Buffer Management Unit
8/01/00
Am79C976
181