PALCE20V8 Datasheet, PDF (8/16 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

AMD
LOGIC DIAGRAM
SKINNYDIP (PLCC and LCC) Pinouts
CLK/I0 1
(2)
I1 2
(3)
0
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
1
0
SG0
11
0X
10
7
I2 3
(4)
11
0X
10
8
15
I3 4
(5)
11
0X
10
16
23
I4 5
(6)
11
0X
10
24
31
I5 6
(7)
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
SL07
SG1
SL06
SG1
SL05
SG1
SL04
SG1
11
10
VCC
00
01
11
0X
DQ
10
Q
10
11
0X
SG0
SL07
11
10
VCC
00
01
DQ
Q
11
0X
10
10
11
0X
SG1 SL06
11
10
VCC
00
01
DQ
Q
11
0X
10
10
11
0X
SG1
SL05
11
10
VCC
00
01
DQ
Q
11
0X
10
10
11
0X
SG1
SL04
(2284)VCC
23 _I13
(27)
22 I/O7
(26)
21 I/O6
(25)
20 I/O5
(24)
19 I/O4
(23)
CLK OE
16491D-6
2-162
PALCE20V8 Family