PALCE20V8 Datasheet, PDF (7/16 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

Power-Up Reset
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE20V8 depend on
whether they are selected as registered or combinato-
rial. If registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALCE20V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Security Bit
A security bit is provided on the PALCE20V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com-
petitors. The bit can only be erased in conjunction with
the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the
PALCE20V8. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independ-
ent of the security bit.
AMD
Programming and Erasing
The PALCE20V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard-
ware. No special erase operation is required.
Quality and Testability
The PALCE20V8 offers a very high level of built-in qual-
ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming and post-programming functional yields in
the industry.
Technology
The high-speed PALCE20V8H is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PCI Compliance
The PALCE20V8H-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special In-
terest Group. The PALCE20V8H-7/10’s predictable tim-
ing ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD
and FPGA architectures without predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
PALCE20V8 Family
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