PALCE20V8 Datasheet, PDF (16/16 Pages) Advanced Micro Devices – EE CMOS 24-Pin Universal Programmable Array Logic

AMD
POWER-UP RESET
The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Parameter
Symbol
tPR
tS
tWL
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Due to the synchronous operation of the power-up reset
and the wide range of ways VCC can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
s The VCC rise must be monotonic.
s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Min
Max
Unit
1000
ns
See Switching
Characteristics
Power
Registered
Output
Clock
4V
tPR
tS
tWL
Power-Up Reset Waveforms
VCC
16491D-16
2-182
PALCE20V8 Family