AM79C965A Datasheet, PDF (53/228 Pages) –

Ti
Ti
T1 T2
T2
T2
T2
T2 T1
T2
Ti Ti
BCLK
ADS
A4–A31
100
100
104
M/IO, D/C
W/R
A2–A3,
100
BE0–BE3
RDYRTN
BRDY
BLAST
D0–D31
AHOLD
HOLD
HLDA
104
To
To
PCnet-32
PCnet-32
Figure 6. Read Cycle with AHOLD
Address is re-driven when AHOLD is de-asserted,
since RDYRTN had not yet arrived.
18219-80
Effect of Bus Preemption
If a bus preemption event occurs during a basic transfer
cycle, then the behavior of the PCnet-32 controller will
depend upon which specific type of access is being
performed. The general response of the PCnet-32
controller is that the current operation will complete
before the PCnet-32 controller relinquishes the bus in
response to the preemption. “Current operation” in this
sense refers to the general PCnet-32 controller
operation, such as “descriptor access”. Note that a
“descriptor access” consists of one or two basic
transfers. Therefore, both transfers of a descriptor
access must be completed before the bus will be
released in response to a preemption. See each of the
sections for Initialization Block DMA transfers,
Descriptor DMA transfers, FIFO DMA transfers and
Linear Burst Transfers for more specific information.
Am79C965A
53