AM79C965A Datasheet, PDF (40/228 Pages) –

In systems where both RDY and RDYRTN (or equiva-
lent) signals are provided, RDY must NOT be tied to
RDYRTN. Most systems now provide for a local device
ready input to the memory controller that is separate
from the CPU READY signal. This second READY sig-
nal is usually labeled as READYIN. This signal should
be connected to the PCnet-32 controller RDY signal.
The CPU READY signal should be connected to the
PCnet-32 controller RDYRTN pin.
In systems where only one READY signal is provided,
then RDY may be tied to RDYRTN.
RDYRTN
Ready Return
Input
RDYRTN functions as an input to the PCnet-32 control
ler. RDYRTN is used to terminate all master accesses
performed by the PCnet-32 controller, except that linear burst
transfers may also be terminated with the BRDY signal.
RDYRTN is used to terminate slave read accesses to
PCnet-32 controller I/O space.
When asserted during slave read accesses to
PCnet-32 controller I/O space, RDYRTN indicates that
the bus mastering device has seen the RDY that was
generated by the PCnet-32 controller and has
accepted the PCnet-32 controller slave read data.
Therefore, PCnet-32 controller will hold slave read data
on the bus until it synchronously samples the RDYRTN
input as active low. The PCnet-32 controller will not
hold RDY valid asserted during this time. The duration
of the RDY pulse generated by the PCnet-32 controller
will always be a single BCLK cycle.
RDYRTN is ignored during slave write accesses to
PCnet-32 controller I/O space. Slave write accesses to
PCnet-32 controller I/O space are considered termi-
nated by the PCnet-32 controller at the end of the cycle
during which the PCnet-32 controller issues an active
RDY.
In systems where both a RDY and RDYRTN (or equiva-
lent) signals are provided, then RDY must not be tied to
RDYRTN. Most systems now provide for a local device
ready input to the memory controller that is separate
from the CPU READY signal. This second READY sig-
nal is usually labeled as READYIN. This signal should
be connected to the PCnet-32 controller RDY signal.
The CPU READY signal should be connected to the
PCnet-32 controller RDYRTN pin.
In systems where only one READY signal is provided,
then the PCnet-32 controller RDY output may be tied to
the PCnet-32 controller RDYRTN input.
W/R
Write/Read Select Input/Output
During slave accesses to the PCnet-32 controller, the
W/R pin, along with D/C and M/IO, indicates the type of
cycle that is being performed.
During PCnet-32 controller bus master accesses, the
W/R pin is an output.
W/R is floated if the PCnet-32 controller is not the
current master on the local bus.
Board Interface
LED1
LED1
Output
This pin is shared with the EESK function. When
operating as LED1, the function and polarity on this pin
are programmable through BCR5. The LED1 output
from the PCnet-32 controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
The LED1 pin is also used during EEPROM Auto-
detection to determine whether or not an EEPROM is
present at the PCnet-32 controller microwire interface.
At the trailing edge of RESET, this pin is sampled to
determine the value of the EEDET bit in BCR19. A
sampled HIGH value means that an EEPROM is
present, and EEDET will be set to ONE. A sampled
LOW value means that an EEPROM is not present, and
EEDET will be set to ZERO. See the “EEPROM Auto-
detection” section for more details.
If no LED circuit is to be attached to this pin, then a pull-
up or pull-down resistor must be attached instead, in
order to resolve the EEDET setting.
LED2
LED2
Output
This pin is shared with the SRDCLK function. When
operating as LED2, the function and polarity on this pin
are programmable through BCR6. The LED2 output
from the PCnet-32 controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
This pin also selects address width for Software
Relocatable Mode. When this pin is HIGH during
Software Relocatable Mode, then the device will be
programmed to use 32 bits of addressing while
snooping accesses on the bus during Software
Relocatable Mode. When this pin is LOW during
Software Relocatable Mode, then the device will be
programmed to use 24 bits of addressing while
snooping accesses on the bus during Software
Relocatable Mode. The upper 8 bits of address will be
assumed to match during the snooping operation when
LED2 is LOW. The 24-bit addressing mode is intended
for use in systems that employ the GPSI signals. For
more information on the GPSI function see section
General Purpose Serial Interface.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in
order to resolve the Software Relocatable Mode ad-
dress setting.
40
Am79C965A