AM79C965A Datasheet, PDF (162/228 Pages) –

individual descriptions of the various 6
BREADE Burst Read Enable. When set, this
DMA transfers.
bit enables Linear Bursting during
PRPCNET is cleared by H_RESET
and is not affected by S_RESET or
STOP.
memory read accesses, where
Linear Bursting is defined to mean
that only the first transfer in the
current bus arbitration will contain
The default setting for this bit will be
an address cycle. Subsequent
PRPCNET = 0. This default value
transfers will consist of data only.
reflects the nature of the CPU’s
However, the entire address bus will
handling of a HOLD request (i.e. the
still be driven with appropriate
CPU has lowest priority). By making
values during the subsequent
this the default setting, the PCnet-32
cycles, but ADS will not be asserted.
controller response to HOLDI is as
When cleared, this bit prevents the
close as possible to the timing of the
part from performing linear bursting
CPU response to HOLD, so that
during read accesses. In no case
minimal design difficulty will be
will the part linearly burst a
created by inserting the PCnet-32
descriptor access or an initialization
controller into the system as the
access.
mediating device between the CPU
and the extension bus chipset.
BREADE is cleared by H_RESET
and is not affected by S_RESET or
8
RES
Reserved bit. Must be written as a
STOP.
ONE. Will be read as a ONE.
Burst Read activity is not allowed
This reserved location is SET by
when the BCLK frequency is >33
H_RESET and is not affected by
MHz. Linear bursting is disabled in
S_RESET or STOP.
VL-Bus systems that operate above
7
DWIO Double Word I/O. When set, this bit
indicates that the PCnet-32
controller is programmed for DWIO
mode. When cleared, this bit
indicates that the PCnet-32
controller is programmed for Word
I/O mode. This bit affects the I/O
Resource Offset map and it affects
the defined width of the PCnet-32
controller’s I/O resources. See the
DWIO and WIO sections for more
details.
this frequency by connecting the
VLBEN pin to either ID(3) (for VL-
Bus version 1.0 systems) or ID(4)
AND ID(3) AND ID(1) AND ID(0) (for
VL-Bus version 1.1 or 2.0 systems).
In Am486-style systems that have
BCLK frequencies above 33 MHz,
disabling the linear burst capability
is ideally carried out through
EEPROM bit programming, since
the EEPROM programming can be
setup for a particular machine’s
architecture. When the VLBEN pin
The PCnet-32 controller will set
has been reset to a ZERO, then the
DWIO if it detects a double-word
BREADE bit will be forced to a value
write access to offset 10h from the
of ZERO. Any attempt to change this
PCnet-32 controller I/O Base
value by writing to the BREADE bit
Address (corresponding to the RDP
location will have no effect.
resource). A double word write
access to offset 10h is the only way
5
that the DWIO bit can be set. DWIO
cannot be set by a direct write to
BCR18.
BWRITE
Burst Write Enable. When set, this
bit enables Linear Bursting during
memory write accesses, where
Linear Bursting is defined to mean
that only the first transfer in the
Once the DWIO bit has been set to
current bus arbitration will contain
a ONE, only a H_RESET can reset
an address cycle. Subsequent
it to a ZERO.
transfers will consist of data only.
DWIO is read only by the host.
However, the entire address bus will
still be driven with appropriate
DWIO is cleared by H_RESET and
values during the subsequent
is not affected by S_RESET or
cycles, but ADS will not be asserted.
STOP.
When cleared, this bit prevents the
162
Am79C965A