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EP1S10 Datasheet, PDF (92/290 Pages) Altera Corporation – Stratix Device Family Data Sheet | |||
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Digital Signal Processing Block
single DSP block can implement two sums or differences from two
18 Ã 18-bit multipliers each or four sums or differences from two 9 Ã 9-bit
multipliers each.
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
(a + jb) à (c + jd) = [(a à c) â (b à d)] + j à [(a à d) + (b à c)]
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a à c) â (b à d)] using one subtractor and the imaginary part
[(a à d) + (b à c)] using one adder, for data widths up to 18 bits. Two
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks. Figure 2â38 shows an 18-bit
two-multipliers adder.
Figure 2â38. Two-Multipliers Adder Mode Implementing Complex Multiply
18
18
A
18
18
18
C
18
B
18
18
D
18
A
18
D
18
B
18
C
DSP Block
36
37
Subtractor
36
(A Ã C) â (B Ã D)
(Real Part)
36
Adder
37
(A Ã D) + (B Ã C)
(Imaginary Part)
36
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18 Ã 18-bit
multipliers or two different sums of two sets of four 9 Ã 9-bit multipliers
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications. Figure 2â39 shows the four multipliers
adder mode.
2â68
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
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