EP1S10 Datasheet, PDF (143/290 Pages) Altera Corporation – Stratix Device Family Data Sheet

Stratix Architecture
shift by the same degree amount. For example, all 10 DQS pins on the top
of the device can be shifted by 90° and all 10 DQS pins on the bottom of
the device can be shifted by 72°. The reference circuits require a maximum
of 256 system reference clock cycles to set the correct phase on the DQS
delay elements. Figure 2–69 illustrates the phase-shift reference circuit
control of each DQS delay shift on the top of the device. This same circuit
is duplicated on the bottom of the device.
Figure 2–69. Simplified Diagram of the DQS Phase-Shift Circuitry
Input
Reference
Clock
Phase
Comparator
Up/Down
Counter
Delay Chains
6
Control Signals
to DQS Pins
See the External Memory Interfaces chapter in the Stratix Device Handbook,
Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 Class I and II, SSTL-2 Class I and II, HSTL Class I and II,
and 3.3-V GTL+ support a minimum setting, the lowest drive strength
that guarantees the I_OH/I_OL of the standard. Using minimum settings
provides signal slew rate control to reduce system noise and signal
overshoot.
Altera Corporation
July 2005
2–119
Stratix Device Handbook, Volume 1