EY1501DI-ADJ Datasheet, PDF (9/13 Pages) Altera Corporation – EY1501DI-ADJ High Performance 1A LDO

Page 9
Power OK Operation
POK is a logic output that indicates the status of V_OUT. The POK flag is an open-drain NMOS that can sink up to 10mA.
It requires an external pull-up resistor typically connected to the V_OUT pin. The POK pin should not be pulled up to a
voltage source greater than V_IN. POK goes low when the output voltage drops below 84% of the nominal output voltage or
if the part is disabled. The POK comparator functions during current limit and thermal shutdown. For applications not using
this feature, connect this pin to ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable.
This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2µA current
source charges up this C_SS and the feedback reference voltage is clamped to the voltage across it. The start-up time is
set by Equation 1.
T_start = -C---^S--2-^S--_μ--x--A-0---.-5--
(EQ. 1)
Equation 2 determines the C_SS required for a specific start-up in-rush current, where V_OUT is the output voltage, C_OUT is
the total capacitance on the output and I_INRUSH is the desired in-rush current.
C_SS = -V---^O-I--_I-^UN---^T-_R--x--_U--C-_S--^O--_H--^U-x--^T-0--x-.--52---V-^μ----A-
(EQ. 2)
The external capacitor is always discharged to ground at the beginning of start-up or enabling.
Output Voltage Selection
An external resistor divider, R1 and R2 as referenced in Figure 1 on page 1, is used to scale the output voltage relative
to the internal reference voltage. The output voltage can be programmed to any level between 0.8V and 5V. The
recommended value for R2 is 500Ω to 5kΩ. R1 is then chosen to satisfy Equation 3.
V_OUT
=
0.5V ×
⎛
⎜
⎝
R-R---^21-
+
⎞
1⎟
⎠
(EQ. 3)
External Capacitor Requirements
External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and
selection of capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The EY1501DI-ADJ applies state-of-the-art internal compensation to keep the selection of the output capacitor simple
for the customer. Stable operation over full temperature, V_IN range, V_OUT range and load extremes are guaranteed for
all capacitor types and values assuming the minimum recommended ceramic capacitor is used for local bypass on
V_OUT. There is a growing trend to use very-low ESR multilayer ceramic capacitors (MLCC) because they can support
fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance
of MLCCs drops with applied voltage, age, and temperature. X7R and X5R dieletric ceramic capacitors are strongly
recommended as they typically maintain a capacitance range within ±20% of nominal voltage over full operating
ratings of temperature and voltage. This output capacitor must be connected to the V_OUT and GND pins of the LDO
with PCB traces no longer than 0.5cm.
Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. The use of Cpb (see
following section) is recommended when only the minimum recommended ceramic capacitor is used on the output.
Please refer to Table 2 for these minimum conditions for various output voltages.
May 2014 Altera Corporation
10039
Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO
May 28, 2014
Rev A