EY1501DI-ADJ Datasheet, PDF (3/13 Pages) Altera Corporation – EY1501DI-ADJ High Performance 1A LDO

Pin Configuration
EY1501DI-ADJ
(10 LD 3x3 DFN)
TOP VIEW
V_{OUT 1}
V_OUT 2
VFB 3
POK 4
GND 5
EPAD
10 ^VIN
9 VIN
8 NC
7 EN
6 SS
Page 3
Pin Descriptions
PIN NUMBER
1, 2
3
4
5
6
7
8
9, 10
-
PIN NAME
V_OUT
VFB
POK
GND
SS
EN
NC
V_IN
EPAD
DESCRIPTION
Regulated output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External Capacitor
Requirements” on page 9 for more details.
This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the output
voltage. In addition, the Power OK circuit uses this input to monitor the output voltage status.
This is an open drain logic output used to indicate the status of the output voltage. Logic low indicates V_OUT is not in
regulation. Must be grounded if not used.
Ground.
External capacitor on this pin adjusts startup ramp and controls inrush current.
V_IN independent chip EN. TTL and CMOS compatible.
No connection. Leave floating.
Input supply. A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External Capacitor
Requirements” on page 9 for more details.
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.
May 2014 Altera Corporation
10039
Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO
May 28, 2014
Rev A