EPXA1 Datasheet, PDF (8/16 Pages) Altera Corporation – Excalibur Device Overview

Excalibur Device Overview
I Peripherals that exchange data using the on-chip dual-port
RAM
I High speed data paths under embedded processor control
I Multi-processor systems, using multiple Nios embedded
processor solutions
I Additional embedded processor interrupt sources and controls
PLD designers can take full advantage of the extensive range of
Altera intellectual property (IP) Megacore^® functions to implement
complex system-on-a-programmable-chip (SOPC) designs in
minimal time but with maximum customization.
The bidirectional bridges and dual-port memory interfaces between
the embedded stripe and the PLD are synchronous to the clock
domain that drives them; however, the embedded processor domain
and the PLD domains are asynchronous. The clock domain for each
side of the interfaces can be optimized for performance. The
bidirectional bridges handle the resynchronization across the
domains and are capable of supporting 32-bit data accesses to the
entire 4-Gbyte address range (32-bit address bus).
The SDRAM memory controller PLL allows users to tune the
frequency of the system clock to the speed of the external memory
implemented in their systems.
Internal Memory
The embedded stripe contains both single-port and dual-port SRAM.
There are two blocks of single-port SRAM; both are accessible to the
AHB masters via an arbitrated interface within memory. Each block
is independently arbitrated, allowing one block to be accessed by one
bus master while the other block is accessed by the other bus master.
Up to 256 Kbytes of single-port SRAM are available, as two blocks of
2 × 128 Kbytes. Each single-port SRAM block is byte-addressable.
The size of the SRAM blocks depends on the device, as shown in
Table 1. Byte, half-word and word accesses are allowed and are
enabled by the slave interface. The behavior of byte and half-word
reads is controlled by the system endianness.
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