EPXA1 Datasheet, PDF (1/16 Pages) Altera Corporation – Excalibur Device Overview

Excalibur Device Overview
May 2002, ver. 2.0
Data Sheet
Features...
Altera Corporation
DS-EXCARM-2.0
I Combination of a world-class RISC processor system with industry-
leading programmable logic on a single device
I Industry-standard ARM922T^™ 32-bit RISC processor core operating
at up to 200 MHz
– ARMv4T instruction set with Thumb^® extensions
– Memory management unit (MMU) included for real-time
operating system (RTOS) support
– Harvard cache architecture with 64-way set associative separate
8-Kbyte instruction and 8-Kbyte data caches
I APEX^™ 20KE-like programmable logic architecture ranging from
100,000 to 1,000,000 gates (see Table 1 on page 3)
I Advanced bus architecture based on advanced microcontroller bus
architecture (AMBA^™) high-performance bus (AHB)
I Embedded programmable on-chip peripherals
– ETM9 embedded trace module to assist software debugging
– Flexible interrupt controller
– Universal asynchronous receiver/transmitter (UART)
– General-purpose timer
– Watchdog timer
I Advanced memory support
– Internal single-port SRAM up to 256 Kbytes
– Internal dual-port SRAM up to 128 Kbytes
– Internal SDRAM controller
- Single data-rate (SDR) and double data-rate (DDR) support
- Up to 512 Mbytes
- Data rates to 133 (266) MHz
– Expansion bus interface (EBI)
- Compatible with industry-standard flash memory, SRAMs,
and peripheral devices
- Four devices, each up to 32 Mbytes
I PLD configuration/reconfiguration possible via the embedded
processor software
I Fully configurable memory map
I Extensive embedded system debug facilities
– SignalTap^™ embedded logic analyzer
– ARM^® JTAG processor debug support
– Real-time data/instruction processor trace
– Background debug monitoring via the IEEE Std. 1149.1 (JTAG)
interface
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