EPXA1 Datasheet, PDF (6/16 Pages) Altera Corporation – Excalibur Device Overview

Excalibur Device Overview
Functional
Description
Two AMBA-compliant AHBs ensure that the embedded processor
activity is unaffected by peripheral and memory operation. Three
bidirectional AHB-to-AHB bridges enable embedded peripherals
and PLD-implemented peripherals to exchange data with the
embedded processor or with other peripherals.
The Excalibur family is supported by the following development
tools:
I SOPC Builder from Altera^®
I Quartus II from Altera
I ADS, GNUPro and other third-party tools
The Excalibur system architecture (embedded processor bus
structure, on-chip memory, and peripherals) combines the
performance advantages of ASIC integration with the flexibility and
time-to-market advantages of PLDs.
The Embedded Processor
The ARM922T is a member of the ARM9 family of processor cores.
Its Harvard architecture, implemented using a five-stage pipeline,
allows single clock-cycle instruction operation through
simultaneous fetch, decode, execute, memory, and write stages.
Figure 3 on page 7 shows the Excalibur embedded processor, the
ARM922T.
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Altera Corporation