EPF10K30AQC240-2 Datasheet, PDF (7/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
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For more information, see the following documents:
■ Configuration Devices for APEX & FLEX Devices Data Sheet
■ BitBlaster Serial Download Cable Data Sheet
■ ByteBlasterMV Parallel Port Download Cable Data Sheet
■ Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000
Devices)
FLEX 10K devices are supported by Altera development systems; single,
integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The Altera
software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and
other interfaces for additional design entry and simulation support from
other industry-standard PC- and UNIX workstation-based EDA tools.
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The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development systems include DesignWare
functions that are optimized for the FLEX 10K architecture.
The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.
See the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet for more information.
Functional
Description
Each FLEX 10K device contains an embedded array to implement
memory and specialized logic functions, and a logic array to implement
general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 2,048 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
Altera Corporation
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