EPF10K30AQC240-2 Datasheet, PDF(58/128 Page) Altera Corporation – Embedded Programmable Logic Device Family

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EPF10K30AQC240-2 Datasheet, PDF (58/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 26. FLEX 10K Device IOE Timing Model

Data-In

Output Data

Delay

tIOD

Clock Enable

Clear

Clock

Output Enable

Data Feedback

into FastTrack

Interconnect

I/O Element

Control Delay

tIOC

I/O Register

Feedback Delay

tIOFD

Input Delay

tINCOMB

I/O Register

Delays

tIOCO

tIOCOMB

tIOSU

tIOH

tIOCLR

tINREG

Input Register Delay

Output

Delays

tOD1

tOD2

tOD3

tXZ

tZX1

tZX2

tZX3

Figure 27. FLEX 10K Device EAB Timing Model

Data-In

Address

Input Register

Clock

Output Register

Clock

EAB Data Input

Delays

tEABDATA1

tEABDATA2

Write Enable

Input Delays

tEABWE1

tEABWE2

EAB Clock

Delay

tEABCLK

Input Register

Delays

tEABCO

tEABBYPASS

tEABSU

tEABH

tEABCH

tEABCL

RAM/ROM

Block Delays

tAA

tDD

tWP

tWDSU

tWDH

tWASU

tWAH

tWO

Output Register

Delays

tEABCO

tEABBYPASS

tEABSU

tEABH

tEABCH

tEABCL

EAB Output

Delay

tEABOUT

Data-Out

Figures 28 shows the timing model for bidirectional I/O pin timing.

Altera Corporation

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