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EPF10K30AQC240-2 Datasheet, PDF (22/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family | |||
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet
During compilation, the Compiler automatically selects the best control
signal implementation. Because the clear and preset functions are active-
low, the Compiler automatically assigns a logic high to an unused clear or
preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
â Asynchronous clear
â Asynchronous preset
â Asynchronous clear and preset
â Asynchronous load with clear
â Asynchronous load with preset
â Asynchronous load without clear or preset
In addition to the six clear and preset modes, FLEX 10K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 10 shows examples
of how to enter a section of a design for the desired functionality.
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Altera Corporation
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