EPF10K30AQC240-2 Datasheet, PDF (27/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
For improved routing, the row interconnect is comprised of a combination
of full-length and half-length channels. The full-length channels connect
to all LABs in a row; the half-length channels connect to the LABs in half
of the row. The EAB can be driven by the half-length channels in the left
half of the row and by the full-length channels. The EAB drives out to the
full-length channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 7 summarizes the FastTrack Interconnect resources available in
each FLEX 10K device.
Table 7. FLEX 10K FastTrack Interconnect Resources
Device
Rows
EPF10K10
3
EPF10K10A
EPF10K20
6
EPF10K30
6
EPF10K30A
EPF10K40
8
EPF10K50
10
EPF10K50V
EPF10K70
9
EPF10K100
12
EPF10K100A
EPF10K130V
16
EPF10K250A
20
Channels per
Row
144
Columns
24
144
24
216
36
216
36
216
36
312
52
312
52
312
52
456
76
Channels per
Column
24
24
24
24
24
24
24
32
40
In addition to general-purpose I/O pins, FLEX 10K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device.
The dedicated inputs can also be used as general-purpose data inputs
because they can feed the local interconnect of each LAB in the device.
However, the use of dedicated inputs as data inputs can introduce
additional delay into the control signal network.
Altera Corporation
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