5M80ZE64I5N Datasheet, PDF (65/166 Pages) Altera Corporation – MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
3–17
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)
Symbol
Parameter
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
C4
C5, I5
5M1270Z/ 5M2210Z
C4
C5, I5
Unit
t_AE
t_EB
t_BE
t_EPMX
t_DCO
t_OE
t_RA
t_OSCS
t_OSCH
Min Max Min Max Min Max Min Max
Minimum erase signal
to address clock hold
0
—
0
—
0
—
0
— ns
time
Maximum delay between
the erase rising edge to
the UFM busy signal
—
960
—
960
—
960
—
960 ns
rising edge
Minimum delay allowed
from the UFM busy
signal going low to
20
—
20
—
20
—
20
— ns
erase signal going low
Maximum length of busy
pulse during an erase
—
500
—
500
—
500
—
500 ms
Delay from data register
clock to data register
—
5
—
5
—
5
—
5
ns
output
Delay from OSC_ENA
signal reaching UFM to
rising clock of OSC
180
—
180
—
180
—
180
— ns
leaving the UFM
Maximum read access
time
—
65
—
65
—
65
—
65 ns
Maximum delay between
the OSC_ENA rising edge
to the erase/program
250
—
250
—
250
—
250
— ns
signal rising edge
Minimum delay allowed
from the
erase/program signal
250
—
250
—
250
—
250
— ns
going low to OSC_ENA
signal going low
May 2011 Altera Corporation
MAX V Device Handbook